1. Field of the Invention
The present invention relates to an apparatus and method for processing Internet Protocol (IP) packet fragmentation to support mobility in a router using a network processor, and more particularly, to an apparatus and method for processing IP packet fragmentation in a routing system using a network processor in order to improve the efficiency of the network processor and to accelerate packet-processing rate.
2. Description of the Related Art
The appearance of new types of Internet services such as voice/data integration and wired/wireless Internet integration has led to an increase in the amount of data to be transmitted and the types of services to support.
Due to such environmental changes, it is substantially impossible to add new functions to or improve performance in Application Specific Integrated Circuit (ASIC) based network devices. The ASIC was developed as part of the Internet, and the ASIC-based network devices are based on the silicon chip. Thus, ASIC-based network devices have limited capacity to process packets. In addition, the network devices developed up to the present use an ASIC switch chip.
In this a case, only the functions provided by the ASIC switch chip can be used. In addition, it has been required to set register values provided by the ASIC switch chip in order to use the functions.
Accordingly, it has been impossible to modify existing functions or implement new functions.
To overcome this, a new type of network device has been introduced, based on a network processor known as a new generation silicon chip.
The network processor is a programmable processor capable of processing packets received via an input user interface (i.e., an input port) in various methods before sending the packets via an output user interface (i.e., an output port). The network processor is a specialized packet processor that can provide high-performance packet-processing capacity at the level of the ASIC while promptly responding to various user demands through a program.
The network processor is a non-memory device that can transmit traffic between ports and act as an intelligent switch based on its programming functions, thereby providing various types of multimedia Internet traffic services in a network device such as a router and a switch. Thus, the network processor can be regarded as a key product of a next generation network device.
In general, the network processor can be configured to include a plurality of micro-engines each including a plurality of threads.
Although a network processor including only one thread can of course be used, it is not generally used due to its inefficiency.
In the related art, an IP packet-processing device for providing mobility to a router uses mobile IP. The mobile IP is a technology required to constantly ensure connection to a terminal having an IP address while the terminal is moving.
Under the current Internet Protocol, a terminal cannot access the Internet when it moves to a different network since its position accessing the Internet is fixed and service is provided on the assumption that an IP fixed on a specific network will be used.
However, the mobile IP system solves the above-described problems and supports mobility based on a double-address system.
This type of mobile IP technology is a fundamental technology that should be realized for the future wireless Internet.
This means that all mobile terminals have to inevitably support mobile IP in consideration that future mobile communication networks will develop into all-IP networks.
This is because Internet protocols are sure to be used as common service protocol in final wire/wireless integrated networks, which are referred to as all-IP networks, and the mobile IP technology is a mobility supported protocol of the Internet protocols.
The mobile IP technology can be applied to a network system such as a router by using a network processor. Below, with reference to the accompanying drawings, a description will be made of one example of the network processor constructed in the network system.
FIG. 1 is a block diagram illustrating an IP packet-processing apparatus including a typical network processor.
The network processor includes sixteen (16) multi-thread packet-processing micro-engines 112 to 127, a core 129, a media switch fabric 100, Static Random Access Memory (SRAM) controllers 102 to 105, Dynamic Random Access Memory (DRAM) controllers 106 to 108, a scratch pad memory 101, and a Peripheral Component Interconnect (PCI) controller 110.
The network processor also includes two engine clusters 100-1 and 100-2, in which the engine cluster 100-1 includes eight (8) micro-engines 112 to 119, and cluster 100-2 includes eight (8) micro-engines 120 to 127.
Threads of the network processor are units of work, to each of which one packet can be allocated.
Each of the micro-engines 112 to 127 is a piece of hardware that performs a variety of network processing functions and processes data at OC-192 (Optical Carrier-192) wire speed.
The core 129 is a 32-bit Reduced Instruction Set Computer (RISC). The core 129 carries out high-performance processes, for example, by processing an exceptional packet, executing a complicated algorithm, maintaining a route table, etc. The SRAM controllers 102 to 105 and the DRAM controllers 106 to 108 perform management for efficient access to SRAMs and DRAMs, in which routing tables or various data structures are stored.
The media switch fabric 100 is connected to a framer, a Media Access Controller (MAC) device or to a switch fabric.
The PCI controller 110 manages communication with an external host processor, other chips, and so on, which are connected via PCT bus. Below, with reference to FIG. 2, a description will be given of a packet process system using the above-described network processor.
FIG. 2 is a block diagram illustrating a conventional network processor.
More specifically, FIG. 2 shows an illustrative application of the network processor on a network in which Internet Protocol version-4 (IPv4) packets and Internet Protocol version-6 (IPv6) packets coexist.
An ingress network processor processes a packet received via an input interface and then forwards the received packet to a Common Switch Interface (CSIX) switch fabric, and an egress network processor processes a packet forwarded from the CSIX switch fabric and then sends the packet to a corresponding output interface.
In this case, the packet-forwarding unit of the input/output interfaces and the network processors is an Ethernet frame, and the packet-forwarding unit of the network processors and the CSIX Switch Fabric is a CSIX frame.
Sixteen (16) micro-engines at the ingress side can be used as a packet receiver 200, a packet classifier or Ethernet decap 201, an IPv6 packet forwarder 202, an IPv4 packet forwarder 203, a CSIX cell scheduler 204, a CSIX queue manager 205, and a CSIX transmitter 206. As egress network processors, a CSIX receiver 210, an Ethernet Address Resolution Protocol (ARP) 211, a packet scheduler 212, a packet queue manager 213, and a packet transmitter 214 can be used.
In order to assist in the understanding of the network processor, respective reference numerals (i.e., 200 through 206 and 210 through 214) of the micro-engines, which are used to perform respective functions, are added to respective functional sections.
In addition, at least one or two micro-engines can be allocated to respective functions in order to process a packet at OC-192 wire speeds based on the respective functions. The remaining micro-engines of the ingress and egress network processors can also be allocated to perform additional functions.
An Ethernet frame, which is input via an input interface of the packet receiver 200, is reassembled.
The packet classifier 201 decapsulates input packets, and classifies types and service grades according to the Quality of Service (QoS) of the packets by referring to the header of the packets.
The packet classifier 201 determines whether a received packet is an IPv4 packet or an IPv6 packet, and based on a result of the determination, outputs the packet to the IPv6 packet forwarder 202 or the IPv4 packet forwarder 203.
In addition, if the received packet is an Address Resolution Protocol (ARP) packet, a control packet associated with a routing protocol, or a packet requiring fragmentation, the packet classifier 201 outputs the packet to the core 129.
The IPv6 packet forwarder 202 and the IPv4 packet forwarder 203 outputs a unicast packet to the packet queue (i.e., the SRAM controller 2) 104 by performing Longest Prefix Match (LPM) on the unicast packet. As a result of the LPM, the output interface of the packet is determined, and resultant information is forwarded on header information of the CSIX frame to the egress network processor. Based on the obtained information, the egress network processor can encapsulate the Ethernet header of the packet or transmit the packet to a corresponding output interface.
The packet classifier 201, the IPv6 packet forwarder 202, and the IPv4 packet forwarder 203 can be commonly referred to as a packet forwarder 207.
The CSIX cell scheduler 204 and the CSIX queue 205 output a packet, forwarded from the IPv6 packet forwarder 202 or the IPv4 packet forwarder 203, to the CSIX transmitter 206 by performing buffering and scheduling on the packet.
The CSIX transmitter 206 encapsulates the CSIX header of the input packet based on a result of LPM and sends the packet to the CSIX switch fabric 20.
The CSIX receiver 210 reassembles a CSIX frame input through the CSIX switch fabric.
The Ethernet ARP 211 adds an Ethernet frame of the CSIX frame header based on output interface information of the CSIX frame header.
The packet scheduler 212 and the packet queue 213 output a packet, forwarded from the Ethernet ARP 211, to the packet transmitter 214 by performing buffering and scheduling on the packet.
The packet transmitter 214 outputs the input packet to a corresponding output interface.
According to the prior art, all packets requiring fragmentation are sent to the core 129.
In the case of providing IP mobility to nodes using the network processor, unlike IP fragmentation for mobile IPv4, IP fragmentation for mobile IPv4 is performed by a router. However, the related art may have the following problems.
First, unlike IP fragmentation for mobile IPv6, IP fragmentation for mobile IPv4 has to be performed by the router in order to provide IP mobility.
In the development of a router, to which a mobile IPv4 function is added (i.e., a router, which is realized by adding a home agent function to mobile nodes), fragmentation requires that a home agent can transmit a packet to the mobile nodes through encapsulation if the mobile nodes are on a foreign network.
In this case, fragmentation occurs when the packet is greater than Maximum Transmission Unit (MTU), which exceeds 1500 bytes in the case of Ethernet.
According to existing research using the network processor under this situation, IP fragmentation has been performed on a control plane.
However, packets may be processed at different rates according to sizes even if the packets are of the same type.
Specifically, some packets, which do not require fragmentation, are processed on a data plane (e.g., the micro-engines 112 through 127 in FIG. 1) and the other packets, which require fragmentation, are processed on a control plane (e.g., the core 129 in FIG. 2).
Second, the amount of packets, which mobile nodes transmit over a network, may occasionally vary, and the size of the packets may occasionally vary as well.
In the router supporting IP mobility, the amount of packets, which do not require fragmentation, may occasionally vary.
Considering that the key function of the Core 129 is a control packet such as an ARP and a routing protocol, a bottle neck effect may occur in the core in proportion to the amount of packets requiring fragmentation.
Accordingly, the network processor is not efficiently used in the related art.